Electrostatic Discharge (ESD) events are occurrences of high electrical potentials of limited energy that can damage a gate oxide of a Field Effect Transistor (FET) by forcing electrical currents to flow through the gate oxide. The flow of the electrical current through the gate oxide can weaken the gate oxide, or the potential can even be sufficiently large to rupture the gate oxide resulting in a so-called “gate short”, or low resistance path to another terminal of the FET. ESD events can be caused by electrostatic discharge from a human body or machines, for example a wafer saw during manufacture of a circuit containing the FET.
To protect the FET, it is known to provide an ESD protection circuit comprising a positive turn-on voltage clamp and a negative turn-on voltage clamp. The positive turn-on voltage clamp is designed to sink ESD current at a preset voltage (and above). In most known ESD protection circuits, whilst the design of the positive turn-on voltage clamp requires considerable attention, the negative turn-on voltage clamp is simply designed to sink ESD current at any voltage below a breakdown voltage of the FET. Typically, the negative turn-on voltage clamp is configured as a reverse-biased diode. A terminal of the ESD protection circuit is coupled to a node associated with the FET to be protected, the node being known, herein, as a protected node.
Among the various RF circuits in existence, power amplifiers have stringent requirements in relation to both ESD protection and RF performance. One example of a power amplifier having such protection and performance requirements is a so-called Laterally Diffused Metal Oxide Semiconductor (LDMOS) power amplifier. For LDMOS power amplifiers, it is known to employ ESD protection circuits comprising a first LDMOS transistor coupled to a source load in a cascode arrangement. The source load comprises a resistor coupled in parallel with a second LDMOS transistor, the second LDMOS transistor being in a grounded-gate configuration. The first LDMOS transistor has a patterned Lightly Doped Drain (LDD) to provide a greater Breakdown Drain Voltage (BVDSS) than provided by a conventional ESD protection structure having a gate and a drain terminal of a FET coupled together. The first LDMOS transistor also reduces a capacitance presented to the protected node. When a positive ESD event occurs, the source load limits current during initial stages of the positive ESD event. In this respect, the load seen at the source terminal of the first LDMOS transistor is a relatively high resistance, R, limiting current flowing through the first LDMOS transistor when the voltage across the first LDMOS transistor is greatest. As current increases, the source voltage of the first LDMOS transistor rises, eventually triggering the diode, formed by coupling the gate and the drain of the second transistor together, to conduct when a negative voltage swing occurs. Consequently, the source to drain PN junction (diode) of the first LDMOS transistor starts to conduct current when around −0.5 Volts is applied across the source to drain PN junction of the first LDMOS transistor.
For LDMOS amplifier circuits, the ESD protection circuit is directly connected to a gate of an LDMOS transistor of the LDMOS amplifier circuit to be protected, i.e. the protected node. Consequently, the ESD protection circuit is held at the same potential as the gate of the LDMOS transistor. When ESD protection circuits were initially designed, typical gate bias voltages for so-called “class AB” operation of LDMOS technology was 4V. As LDMOS technology has evolved, each new generation of LDMOS transistor has had a lower gate threshold voltage than previous generations. In this respect, a typical gate bias voltage for class AB operation for the latest generation of LDMOS transistors is currently 2.5V. For applications for Doherty or so-called “class B” and “class C” amplifiers, the gate bias voltage can be even lower, for example the gate bias voltage can be as low as 1V. For gate bias voltages of 2.5V and below, as RF input drive signal levels increase, gate potential swing can become negative and reach −0.5V and below. This results in current flowing through the gate of the LDMOS transistor of the LDMOS amplifier circuit and hence either poor RF circuit performance due to clipping of the RF input drive signal or outright failure of the ESD protection circuit, because a high level of current is shunted through the ESD protection circuit so as to cause the ESD protection circuit to fail, i.e. fuse.